1. Field of the Invention
The present invention relates to a semiconductor integrated circuit used in a microprocessor and in particular, to an information processing device, which mounts a hardware accelerator for translating codes in a given intermediate language into instructions specific to each of microprocessor types.
2. Description of Related Art
Recently, applications written in the Java™ language have been increasingly used in cell phones and mobile computers. Java developed by Sun Microsystems is an object-oriented programming language analogous to C++. Note that “Java” is a registered trademark of Sun Microsystems. Java has been widely accepted for such a reason that Java programs are executed after being translated from the codes in the intermediate language into the instructions specific to each of microprocessor CPU types using a virtual machine. With the virtual machine mounted, any CPU has a high portability because Java applications can be executed whatever be the CPU type. Note that the intermediate language describes the codes, also called bytecodes, compiled for obtaining the executable Java object program.
As commonly known, since the virtual machine (hereafter, simply referred to as “VM”), which is generally provided by software (hereafter, simply referred to as “soft VM”), interprets and executes individual bytecodes using an interpreter, causing its processing speed to slow, an attempt to speed up processing is made by executing frequently used bytecodes on hardware in some cases. One of these cases is disclosed in PC 2000-507015 (WO 98/21655, PCT/U.S. 07/20980).
Prior to submission of the present application, the inventors of the present invention evaluated consistency between the result from translation of the intermediate language codes (bytecodes) by soft VM and that by hardware typically as in the Java language mentioned above. This means that if hardware is used in translating the bytecodes into instructions in the target language specific to the computer (hereafter, simply referred to as CPU instructions), it is ideal that all the bytecodes can be translated by hardware. Some bytecodes, however, have complex functions and when they are translated, a large amount of CPU codes may be generated ranging from several tens to several hundreds. For this reason, since it is difficult to execute all the bytecodes by hardware, only some of bytecodes are processed by it. This avoids scaling up of hardware involved in executing all the bytecodes by hardware only. Thus, it is required to switch between hardware processing and software processing as appropriate when bytecodes are translated.
FIGS. 9A and 9B show schematic views explaining how to switch between hardware processing and software processing according to the present invention. FIG. 9A shows application software APP1 (the bytecodes) and application software APP2 (the CPU codes), both of which are located on a memory map. Since APP2 is described by a CPU instruction NC, it can be directly executed with no need for translation.
On the contrary, before APP1 (the bytecode) can be executed, it must have been translated into its corresponding CPU instructions. The instructions used in APP1 may be grouped into the following three types from the standpoint of translation and execution. Specifically, C1 is an instruction in the first group of bytecodes and translated by soft VM. This means that C1 is the instruction not supported by a hardware translator. The next C2 is the instruction in the second group of bytecodes and translated by the hardware translator. The third C3 is the instruction in the third group of bytecodes and indicates an action to be taken when a Java run-time exception occurs during execution. The Java run-time exception occurs when the semantic constraint of the Java language is violated. For example, the exception, which occurs when an integer is divided by a divisor 0 (zero), is defined as Arithmetic Exception. When the Java run-time exception is detected, the control is transferred to soft VM and the exception is processed by an error handling routine integrated in soft VM. Since neglecting C3 may induce runaway of the microcomputer itself, any correct error handling action must always be taken.
FIG. 9B shows execution status of a group of C1 to C3 instructions. S indicates the process executed by soft VM while H indicates that by hardware. At this point, to switch from S to H, a hardware start-up process ACT_H must be added and to switch from H to S, a hardware end and soft VM start-up process END_H must be added. The inventors are aware that if switching between S and H are frequently performed using enable and disable instructions for enabling and disabling execution by hardware or if the Java exception occurs during execution by hardware, ACT_H or END_H might occur, causing the processing speed to slow.